The present invention relates to a semiconductor device constituted of a semiconductor device chip mounted on a packaging substrate in a flip chip method, and more specifically to such a semiconductor device and a method for fabricating the same, which generalize or standardize a core substrate included in the packaging substrate thereby to reduce the cost of the semiconductor device and to simplify the fabrication of the semiconductor device.
For the purpose of microminiaturizing a semiconductor device with a high integration density, a BGA (Ball Grid Array) type semiconductor device has been proposed which includes a semiconductor device chip mounted and packaged on a packaging substrate. In brief, the BGA type semiconductor device is constructed by mounting a device chip on a front surface of a packaging substrate which has a multilayer wiring structure and which has a number of solder balls located in the form of an array on a back surface of the packaging substrate so that the packaged semiconductor device can be mounted on a mother board by utilizing the solder balls.
For example, referring to FIG. 9, there is shown a diagrammatic sectional view of the BGA package disclosed in Japanese Patent Application Pre-examination Publication No. JP-A-09-064236. A packaging substrate 101 has a multilayer wiring structure including a number of wiring layers 102 laminated as shown and electrically interconnected through via holes 103 formed in unitary substrate layers. Mounting pads 104 are formed of an uppermost wiring layer of the packaging substrate 101. Flip chip terminals 106 of a device chip 105 are connected facedown to the mounting pads 104. In addition, electrodes 107 are formed of a lowermost wiring layer of the packaging substrate 101 and a solder ball 108 is bonded on each of the electrodes 107.
In this BGA package, a lead frame is no longer necessary, and the size of the package can be reduced to a size similar to that of the device chip. Therefore, the BGA package is effective in realizing the microminiaturization and the high integration density of the semiconductor device.
In this type of BGA semiconductor device, the packaging substrate has the multilayer wiring structure in order to cause the location of the flip chip terminals of the device chip to correspond to the location of the solder balls of the packaging substrate. In order to provide the multilayer wiring structure capable of achieving this purpose, the packaging substrate having a core substrate provided with buildup wiring layers.
Referring to FIG. 10, there is shown a diagrammatic sectional view of the packaging substrate disclosed in Japanese Patent Application Pre-examination Publication No. JP-A-2000-260893. A core substrate 201 is constituted of an insulating substrate 202 having opposite surfaces having given patterns of wiring layers 203 and 204, respectively, which are electrically interconnected by via holes 205 penetrating through the core substrate 201. On the opposite surfaces of the core substrate 201, an upper buildup layer 210 and a lower buildup layer 220 are formed respectively. The upper buildup layer 210 is constituted of two elementary insulating layers 211 and 213 and two wiring layers 212 and 214 laminated as shown. Similarly, the lower buildup layer 220 is constituted of two elementary insulating layers 221 and 223 and two wiring layers 222 and 224 laminated as shown.
Mounting pads, which correspond to the flip chip terminals of the device chip, are formed of the wiring layer 214 of the upper buildup layer 210. Electrodes for the solder balls are formed of the wiring layer 224 of the lower buildup layer 220.
With the multilayer wiring structure mentioned above, the wiring layers 212 and 214 of the upper buildup layer 210 and the wiring layers 222 and 224 of the lower buildup layer 220 are electrically interconnected through via holes 215, 216, 225 and 226 formed in the buildup layers and the via holes 205 in the core substrate 201. Thus, a location of the solder balls can be adjusted independently of the location of the flip chip terminals of the device chip. For example, the same location of the solder balls can be realized even for device chips having different locations of the flip chip terminals, so that the device chips having different locations of the flip chip terminals can be mounted on the same mother board. Incidentally, the core substrate is not limited to the structure mentioned above, but can have a structure having an insulating substrate having opposite surfaces each provided with two buildup wiring layers.
In the prior art BGA type semiconductor device having the packaging substrate having the buildup layers shown in FIG. 10, the electrodes for the solder balls formed on the lower buildup layer 220 are directly determined to correspond to corresponding electrodes of the mother board. However, the mounting pad pattern formed on the upper buildup layer 210 is required to be individually determined to correspond for device chips of different kinds, for example, having different chip sizes or different patterns of flip chip terminals. Therefore, at the time of fabricating the packaging substrate, it was necessary to design the upper buildup layer 210 in accordance with the kind of the device chip to be packaged, and also to design the location of the via holes 205 in the core substrate 201 in accordance with the designed specification of the upper buildup layer 210 so as to electrically connect to the lower buildup layer 220.
As mentioned above, at each time a different kind of device chip is to be mounted, the prior art prior art BGA type semiconductor device requires to newly design and form the core substrate and the buildup layer in accordance with the kind of the device chip to mounted. However, the core substrate has the wiring layers formed on the surfaces of the insulating substrate and the via holes formed in the insulating substrate, as mentioned above. For fabricating the core substrate, it is necessary to form the necessary through holes in the insulating substrate, and to carry out an electroless plating to deposit a conducting film covering the opposite surfaces of the insulating substrate and an inner wall surface of each through hole, and then, to fill each through hole with a resin so as to prevent incursion of air, and further to pattern the conducting film deposited on the opposite surfaces of the insulating substrate. Thereafter, the buildup layers are formed on the opposite surfaces of the core substrate thus formed.
Therefore, the ratio of the number of steps for forming the core substrate to the number of total steps for forming the packaging substrate is relatively large, and accordingly, the TAT (turn around time) in the design and fabrication of the packaging substrate becomes long, with the result that the time for fabricating the packaged semiconductor device becomes long and the cost of the packaged semiconductor device correspondingly becomes high.
Accordingly, it is an object of the present invention to provide a semiconductor device and a method for fabricating the same, which have overcome the above mentioned problems of the prior art.
Another object of the present invention is to provide a semiconductor device and a method for fabricating the same, capable of reducing the number of steps for forming the packaging substrate, thereby to reduce the term and the cost for fabricating the packaged semiconductor device.
The above and other objects of the present invention are achieved in accordance with the present invention by a packaged semiconductor device comprising a packaging substrate having a core substrate having core wiring layers formed on opposite surfaces thereof, respectively, and a plurality of core via holes in the core substrate for mutually electrically connecting the core wiring layers, and upper and lower buildup layers formed on an upper surface and a lower surface of the core substrate, respectively, and each having a wiring layer, a semiconductor device chip mounted on mounting pads formed on the upper buildup layer, and externally connecting electrodes formed on the lower buildup layer, wherein the position of the core via holes in the core substrate is standardized, and the mounting pads formed on the upper buildup layer are located to coincide connection terminals of the semiconductor device chip of a different kind.
In a preferred embodiment of the packaged semiconductor device, the core substrate includes an insulating substrate having opposite upper and lower surfaces each having at least one core wiring layer formed thereon. The mounting pads are electrically connected to the core wiring layer formed on the upper surface of the insulating substrate through buildup via holes formed in the upper buildup layer, and the externally connecting electrodes are electrically connected to the core wiring layer formed on the lower surface of the insulating substrate through buildup via holes formed in the lower buildup layer.
In another preferred embodiment of the packaged semiconductor device, each of the upper buildup layer and the lower buildup layer includes a plurality of laminated wiring layers. The mounting pads are formed of an uppermost wiring layer of the plurality of laminated wiring layers in the upper buildup layer, and a lowermost wiring layer of the plurality of laminated wiring layers in the upper buildup layer is connected to the core via holes, and the externally connecting electrodes are formed of a lowermost wiring layer of the plurality of laminated wiring layers in the lower buildup layer, and an uppermost wiring layer of the plurality of laminated wiring layers in the lower buildup layer is connected to the core via holes.
According to another aspect of the present invention, there is provided a method for fabricating a packaged semiconductor device, comprising the steps of:
forming a packaging substrate having a core substrate having core wiring layers formed on opposite surfaces thereof, respectively, and a plurality of core via holes formed in the core substrate at standardized positions for mutually electrically connecting the core wiring layers, an upper buildup layer formed on an upper surface of the core substrate and having a plurality of mounting pads, and a lower buildup layer formed on a lower surface of the core substrate and having a plurality of externally connecting electrodes; and
mounting a semiconductor device chip on the mounting pads,
wherein in a step for forming the upper buildup layer, a location pattern of the mounting pads formed on the upper buildup layer is determined in accordance with the kind of the semiconductor device chip to be mounted, to coincide connection terminals of the semiconductor device chip to be mounted.
In a preferred embodiment of the method for fabricating a packaged semiconductor device, each of the upper buildup layer and the lower buildup layer has one wiring layer, and at the same time as the location pattern of the mounting pads is determined, a pattern shape of a wiring layer formed at the same level as the mounting pads, a pattern shape of the core wiring layer formed on the upper surface of the core substrate, and a location position of via holes formed in the upper buildup layer for connecting between the core wiring layer formed on the upper surface of the core substrate and the wiring layer formed at the same level as the mounting pads are determined.
In another preferred embodiment of the method for fabricating a packaged semiconductor device, each of the upper buildup layer and the lower buildup layer includes a plurality of laminated wiring layers, and, in a step for forming the upper buildup layer, the mounting pads are formed of an uppermost wiring layer of the plurality of laminated wiring layers in the upper buildup layer, and a location position of the mounting pads is determined in accordance with the kind of the semiconductor device chip to be mounted, and simultaneously, a pattern shape of the uppermost wiring layer extending from the mounting pads, a pattern shape of an underlying wiring layer located under the uppermost wiring layer, and a location position of via holes formed in the upper buildup layer for connecting between the uppermost wiring layer and the underlying wiring layer are determined.
With the above mentioned arrangement, semiconductor device chips having different chip sizes can be mounted on the packaging substrate without changing the position of core via holes formed in the core substrate, by changing the mounting pads of the upper buildup layer and the wiring patterns extending form the mounding pads, in accordance with a semiconductor device chip having a different chip size to be mounted, and also by correspondingly changing the position of the via holes of the upper buildup layer.
Thus, by using the general-purpose core substrate having the standardized positions of core via holes, it is possible to mount semiconductor device chips having different chip sizes, and furthermore, to realize packaged semiconductor devices having different external sizes. As a result, the number of steps for designing and fabricating the core substrate can be reduced, so that the term and the cost for fabricating the packaged semiconductor devices can be reduced.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.